A high performance 0.6 mu m BiCMOS SRAM technology with emitter-base self-aligned bipolar transistors and retrograde well for MOS transistors

The described technology uses a quintuple poly-Si and double-metal process architecture. The emitter and base of a bipolar transistor are self-aligned. The retrograde well for MOS transistors and the P isolation for bipolar transistors are formed by using high-energy ion implantation, while the concentration of the collector is determined by an N epitaxial layer only. As thick oxide remains at the base region before sidewall formation of MOS transistors, an ideal base current flows. The delay times of ECL, CMOS, and BiNMOS are 87 ps, 97 ps, and 130 ps, respectively. BiNMOS has a speed advantage over CMOS down to 2.5 V. A 5-ns 256 K (32 K*8) TTL SRAM has been fabricated with a 0.6- mu m BiCMOS SRAM technology.<>