Prognosis of Manufacturing of a Two-Level Current-Mode Logic Gate in Latch Based on Heterostructures to Increase Density of their Elements with Account Miss-Match Induced Stress and Porosity of Materials on Technological Process. On Approach for Optimization of Manufacturing

In the present time several actual problems of the solid state electronics (such as increasing of performance, reliability and density of elements of integrated circuits: diodes, field-effect and bipolar transistors) are intensively solving [1-6]. To increase the performance of these devices it is attracted an interest determination of materials with higher values of charge carriers mobility [7-10]. One way to decrease dimensions of elements of integrated circuits is manufacturing them in thin film heterostructures [3-5,11]. In this case it is possible to use inhomogeneity of heterostructure and necessary optimization of doping of electronic materials [12] and development of epitaxial technology to improve these materials (including analysis of mismatch induced stress) [13-15]. An alternative approaches to increase dimensions of integrated circuits are using of laser and microwave types of annealing [16-18].