{"title":"多芯片模块VLSI互连的良率分析与优化","authors":"Qi-Jun Zhang, M. Nakhla","doi":"10.1109/MCMC.1993.302134","DOIUrl":null,"url":null,"abstract":"A CAD approach integrating multidimensional correlated Monte-Carlo analysis and generalized l/sub 1/ optimization with lossy transmission line network simulations is presented. It is implemented in a CAD framework for statistical analysis and yield optimization of high-speed VLSI interconnects. Physical/geometrical based hierarchical Monte-Carlo analysis and yield optimization examples are presented.<<ETX>>","PeriodicalId":143140,"journal":{"name":"Proceedings 1993 IEEE Multi-Chip Module Conference MCMC-93","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"Yield analysis and optimization of VLSI interconnects in multichip modules\",\"authors\":\"Qi-Jun Zhang, M. Nakhla\",\"doi\":\"10.1109/MCMC.1993.302134\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A CAD approach integrating multidimensional correlated Monte-Carlo analysis and generalized l/sub 1/ optimization with lossy transmission line network simulations is presented. It is implemented in a CAD framework for statistical analysis and yield optimization of high-speed VLSI interconnects. Physical/geometrical based hierarchical Monte-Carlo analysis and yield optimization examples are presented.<<ETX>>\",\"PeriodicalId\":143140,\"journal\":{\"name\":\"Proceedings 1993 IEEE Multi-Chip Module Conference MCMC-93\",\"volume\":\"37 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-03-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 1993 IEEE Multi-Chip Module Conference MCMC-93\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MCMC.1993.302134\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 1993 IEEE Multi-Chip Module Conference MCMC-93","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MCMC.1993.302134","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Yield analysis and optimization of VLSI interconnects in multichip modules
A CAD approach integrating multidimensional correlated Monte-Carlo analysis and generalized l/sub 1/ optimization with lossy transmission line network simulations is presented. It is implemented in a CAD framework for statistical analysis and yield optimization of high-speed VLSI interconnects. Physical/geometrical based hierarchical Monte-Carlo analysis and yield optimization examples are presented.<>