优先仲裁器的新设计

Proceedings of the Sixteenth National Radio Science Conference. NRSC'99 (IEEE Cat. No.99EX249) Pub Date : 1999-02-23 DOI:10.1109/NRSC.1999.760897

H. T. Bahbouh, A. Khalil, A. Salama

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引用次数: 0

摘要

许多带有异步输入的数字电路即使在所有元件都没有故障的情况下也容易发生故障。当它们的输入具有临界时序组合时，它们可能由于亚稳操作而失效。本文提出了一种新的优先仲裁器结构来解决亚稳态问题。通过SPICE仿真验证了该方法的性能和正确性。结果表明，与其他仲裁器相比，这种新设计对亚稳操作具有更好的免疫力。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Novel design of priority arbiter

Many digital circuits with asynchronous inputs are susceptible to failure even when all their components are fault-free. They may fail as a result of metastable operation when their inputs have critical timing combinations. This paper addresses a novel priority arbiter architecture to solve the metastability problem. SPICE simulation is used to verify its performance and correctness. In contrast to other arbiters, the results showed that this new design has better immunity against metastable operation.

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Proceedings of the Sixteenth National Radio Science Conference. NRSC'99 (IEEE Cat. No.99EX249)

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