Research of PCB Parasitic Inductance in the GaN Transistor Power Loop

Gallium Nitride (GaN) transistor in the high power density converter application is widely researched nowadays. High frequency switching largely reduces the volume of passive components and also leads to challenges in the PCB layout. Parasitic inductance within the critical power loop should be minimized to fully harness the potential of GaN transistor fast switching capability. This paper provides a numerical method for the power loop inductance quantification. Experimental results on the synchronous buck converter are given to validate the estimation accuracy.