{"title":"边界扫描描述语言在设计中的应用","authors":"Dick Chiles, J. DeJaco","doi":"10.1109/TEST.1991.519752","DOIUrl":null,"url":null,"abstract":"Starting with a VHDL description of a chip without IEEE 1149.1 Boundary Scan, the computer program described here creates a structural VHDL design for the boundary scan circuitry, using pre-defined boundary scan cells, pin driverlreceivers, and TAP Controller. One output file from the program is the Boundary Scan Description Language (BSDL) for the chip. Changes may be made to the boundary scan circuitry by manually editing the BSDL and rerunning the program with BSDL as an input file. Controller","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"70 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"USING BOUNDARY SCAN DESCRIPTION LANGUAGE IN DESIGN\",\"authors\":\"Dick Chiles, J. DeJaco\",\"doi\":\"10.1109/TEST.1991.519752\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Starting with a VHDL description of a chip without IEEE 1149.1 Boundary Scan, the computer program described here creates a structural VHDL design for the boundary scan circuitry, using pre-defined boundary scan cells, pin driverlreceivers, and TAP Controller. One output file from the program is the Boundary Scan Description Language (BSDL) for the chip. Changes may be made to the boundary scan circuitry by manually editing the BSDL and rerunning the program with BSDL as an input file. Controller\",\"PeriodicalId\":272630,\"journal\":{\"name\":\"1991, Proceedings. International Test Conference\",\"volume\":\"70 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-10-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1991, Proceedings. International Test Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TEST.1991.519752\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1991, Proceedings. International Test Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.1991.519752","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
USING BOUNDARY SCAN DESCRIPTION LANGUAGE IN DESIGN
Starting with a VHDL description of a chip without IEEE 1149.1 Boundary Scan, the computer program described here creates a structural VHDL design for the boundary scan circuitry, using pre-defined boundary scan cells, pin driverlreceivers, and TAP Controller. One output file from the program is the Boundary Scan Description Language (BSDL) for the chip. Changes may be made to the boundary scan circuitry by manually editing the BSDL and rerunning the program with BSDL as an input file. Controller
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