P-type tunneling FET on Si (110) substrate with anisotropic effect

The promising potential of tunneling FETs (TFETs) for steep switch behavior with gate controlled band-to-band tunneling (BTBT) mechanism has attracted much attention for supply voltage (VDD) scaling and power consumption next generation CMOS [1, 2]. However, the challenge for TFETs is lower drive currents as compare with MOSFET due to a high conductance resistance while reverse bias. Tunneling FETs (TFETs) operates with band-to-band tunneling current that change with the channel potential more abruptly than thermionic emission current. In order to obtain high ION without sacrificing IOFF, and the high-k dielectric and metal gate are integrated as gate stack. To obtain high quality and avoid crystallizing of high-K layer, the gate last process was performed in this work. For N-TFET, much works have been reported on the SS improvement [4, 5]. For P-TFET, Bhuwalka et al. reported the ambipolar working of vertical TFET with negative gate bias, which obtain SS < 60mV/dec [6, 7]. In this work, we will demonstrate HK/MG (high-K/metal gate) P-TFET with the gate last process, and discuss the anisotropic effect on (110) substrate.