一种用于微处理器配电网络通信的数据恢复块设计

2008 4th IEEE International Conference on Circuits and Systems for Communications Pub Date : 2008-05-26 DOI:10.1109/ICCSC.2008.155

V. Chawla, R. Thirugnanam, D. Ha, T. M. Mak

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引用次数: 6

摘要

我们提出使用微处理器的配电网络(PDN)对内部节点进行无所不在的访问进行测试/调试，并展示了脉冲超宽带(UWB)通信的适用性。本文设计了一种数据恢复模块，用于从叠加在微处理器电源线上的超宽带脉冲中恢复数据。讨论了基于实测PDN特性的数据恢复块设计的考虑因素。该电路在台积电0.18 um CMOS工艺上实现，仿真结果表明，在1.8 V电源和200 MHz脉冲重复频率下，电路功耗为4.42 mW。

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Design of a Data Recovery Block for Communications over Power Distribution Networks of Microprocessors

We proposed the use of power distribution network (PDN) of a microprocessor for ubiquitous access of internal nodes for test/debug and showed the suitability of impulse ultra-wideband (UWB) communications for the purpose. This paper presents design of a data recovery block to recover data from UWB impulses superposed on a power line of a microprocessor. Considerations for data recovery block design based upon measured PDN characteristics have been discussed. The proposed circuit was implemented in TSMC 0.18 um CMOS process, and simulations show that it consumes 4.42 mW when operating from a 1.8 V supply and at a pulse repetition rate of 200 MHz.

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2008 4th IEEE International Conference on Circuits and Systems for Communications

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