pld的自动测试技术

Proceedings of the Nineteenth National Radio Science Conference Pub Date : 2002-11-07 DOI:10.1109/NRSC.2002.1022649

A. Elsayed, M. Elbably, H. Elbolok

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引用次数: 3

摘要

可编程逻辑器件(pld)广泛应用于许多设计电路的硬件实现中。故障行包含许多可配置逻辑块(clb)，识别故障行是许多研究人员的目标。在这项研究中提出了一项新技术。所提出的技术的主要目的集中在确定学院CLB在FPGA(现场可编程门阵列)芯片中的位置。

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An automatic testing technique for PLDs

The programmable logic devices (PLDs) are widely used in the hardware implementation of many designed circuits. Identifying the faulty row, which contains many configurable logic blocks (CLBs) was the aim of many researchers. A. new technique is proposed in this research. The main aim of the proposed technique concentrates on identifying the location of the faculty CLB in FPGA (field programmable gate array) chips.

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Proceedings of the Nineteenth National Radio Science Conference

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