Gate Lifetime of P-Gate GaN HEMT in Inductive Power Switching

The small gate overvoltage margin is a crucial concern in applications of GaN Schottky-type p-gate high electron mobility transistors (SP-HEMTs). The parasitic inductance of the gate loop can induce repetitive gate-voltage ($V_{G}$) spikes during the device turn-on transients. However, the gate lifetime of the GaN SP-HEMTs under $V_{G}$ overshoot in power converters still remains unclear. We fill this gap by developing a new circuit method to measure the gate switching lifetime. The method features several capabilities: 1) LC-resonance-like $V_{G}$ overshoots with pulse width down to 20 ns and $dV_{G} /dt$ up to 2 V/ns; 2) adjustable power loop condition including the drain-source grounded (DSG) as well as the hard switching (HSW); and 3) repetitive switching test at an adjustable switching frequency ($f_{\text{sw}}$). We use this method to test over 150 devices, and found that the gate lifetimes under a certain peak magnitude of $V_{G}$ overshoot ($V_{\mathrm{G}(\text{PK})}$) can be fitted by both Weibull and Lognormal distributions. The gate lifetime is primarily determined by the number of switching cycles and is higher under the HSW than under the DSG conditions. Finally, the max $V_{\mathrm{G}(\text{PK})}$ for 10-year gate lifetime is predicted under different $f_{\text{SW}}$ in both DSG and HSW conditions. The results provide direct reference for GaN SP-HEMT's converter applications and a new method for the device gate qualification.