{"title":"了解和控制晶圆片级芯片级封装的晶圆表面污染- Wiljelm Carl K. Olalia","authors":"Kristine B. Bongat","doi":"10.23919/ISSM.2017.8089087","DOIUrl":null,"url":null,"abstract":"In a semiconductor manufacturing processes such as Wafer Level Chip Scale Package, yield is one of the Key Performance Indicator. Yield is also an indicator for Quality, Productivity and OEE. If the yield is below the limits or cut-off, it said to be that there is a sign of poor quality since the process is rejecting Wafer or Dice affected by different defects either by Electrical or by Visual Mechanical. One of the ON's Key Customer Expectation Requirements in terms of Product Quality is “Zero Defects”. There is an equivalent cost for each poor quality computed by number of dice or ppm. In terms of Productivity, Low Yield product is being hold at the process before moving the lot to next process or shipping out. The additional time required to Engineer on analyzing the problem resulted to longer cycle time or queuing. ON's Key Customer Expectation Requirements in terms of Service is 90–100% On Time Delivery. Lastly, for the OEE, definitely low yield will directly affect the overall equipment efficiency since one of the parameter when computing the OEE is the Good Parts from the product on top of the Ideal Cycle Time and Earned Hours from the Master Plan. To conclude, improving the yield will also improve the Quality, Productivity and Cycle Time.","PeriodicalId":280728,"journal":{"name":"2017 Joint International Symposium on e-Manufacturing and Design Collaboration (eMDC) & Semiconductor Manufacturing (ISSM)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Understanding and controlling wafer surface contamination at wafer level chip scale package — Wiljelm Carl K. Olalia\",\"authors\":\"Kristine B. Bongat\",\"doi\":\"10.23919/ISSM.2017.8089087\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In a semiconductor manufacturing processes such as Wafer Level Chip Scale Package, yield is one of the Key Performance Indicator. Yield is also an indicator for Quality, Productivity and OEE. If the yield is below the limits or cut-off, it said to be that there is a sign of poor quality since the process is rejecting Wafer or Dice affected by different defects either by Electrical or by Visual Mechanical. One of the ON's Key Customer Expectation Requirements in terms of Product Quality is “Zero Defects”. There is an equivalent cost for each poor quality computed by number of dice or ppm. In terms of Productivity, Low Yield product is being hold at the process before moving the lot to next process or shipping out. The additional time required to Engineer on analyzing the problem resulted to longer cycle time or queuing. ON's Key Customer Expectation Requirements in terms of Service is 90–100% On Time Delivery. Lastly, for the OEE, definitely low yield will directly affect the overall equipment efficiency since one of the parameter when computing the OEE is the Good Parts from the product on top of the Ideal Cycle Time and Earned Hours from the Master Plan. To conclude, improving the yield will also improve the Quality, Productivity and Cycle Time.\",\"PeriodicalId\":280728,\"journal\":{\"name\":\"2017 Joint International Symposium on e-Manufacturing and Design Collaboration (eMDC) & Semiconductor Manufacturing (ISSM)\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 Joint International Symposium on e-Manufacturing and Design Collaboration (eMDC) & Semiconductor Manufacturing (ISSM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/ISSM.2017.8089087\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Joint International Symposium on e-Manufacturing and Design Collaboration (eMDC) & Semiconductor Manufacturing (ISSM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/ISSM.2017.8089087","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Understanding and controlling wafer surface contamination at wafer level chip scale package — Wiljelm Carl K. Olalia
In a semiconductor manufacturing processes such as Wafer Level Chip Scale Package, yield is one of the Key Performance Indicator. Yield is also an indicator for Quality, Productivity and OEE. If the yield is below the limits or cut-off, it said to be that there is a sign of poor quality since the process is rejecting Wafer or Dice affected by different defects either by Electrical or by Visual Mechanical. One of the ON's Key Customer Expectation Requirements in terms of Product Quality is “Zero Defects”. There is an equivalent cost for each poor quality computed by number of dice or ppm. In terms of Productivity, Low Yield product is being hold at the process before moving the lot to next process or shipping out. The additional time required to Engineer on analyzing the problem resulted to longer cycle time or queuing. ON's Key Customer Expectation Requirements in terms of Service is 90–100% On Time Delivery. Lastly, for the OEE, definitely low yield will directly affect the overall equipment efficiency since one of the parameter when computing the OEE is the Good Parts from the product on top of the Ideal Cycle Time and Earned Hours from the Master Plan. To conclude, improving the yield will also improve the Quality, Productivity and Cycle Time.