一个1.0 ns访问770 MHz的36 Kb SRAM宏

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI:10.1109/VLSIC.1999.797253

T. Uetake, Y. Maki, T. Nakadai, K. Yoshida, M. Susuki, R. Nanjo

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引用次数: 10

摘要

只提供摘要形式。采用0.18 /spl mu/m CMOS低成本ASIC技术，开发了一个1.0 ns存取、770 MHz、36 Kb SRAM宏。实现这种高性能的关键技术是全动态快速字驱动电路、无噪声位线负载电路和高速双模感测放大电路。使用编译器可以自动生成高达2 Kword x 72位的字位大小。

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A 1.0 ns access 770 MHz 36 Kb SRAM macro

Summary form only given. A 1.0 ns access, 770 MHz, 36 Kb SRAM macro using a 0.18 /spl mu/m CMOS low cost ASIC technology was developed. Key technologies used to achieve this high performance are full dynamic fast word driver circuits, noise free bit line load circuits and high speed dual-mode sense amplifier circuits. The word-bit size up to 2 Kword x 72 bit can be generated automatically by using a compiler.

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来源期刊

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)

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