Hardware microcontrol schemes using PLAs

Four new schemes for microprogram control design with programmable logic arrays (PLAs) are proposed. The general structure of the first three schemes consists of three units namely, the microcode memory (ROM), the microsequencer PLA, and a register-counter. The basic idea is to store only branching information, by means of control constructs or transactions, in the PLA(s). These transactions have simple jump-type or continue-type formats with only the jump being embedded in PLA(s). A more general structure, scheme 4, is also proposed with the objective to generate powerful transactions implementing complex control constructs, such as microsubroutines, nested microprogram loops, etc., in addition to multiway branch capability. These transactions contain horizontally formatted directive bits and, hence, they exhibit a measure of parrallelism. The aim is to transform the sequencing structure of a microprogram into a “program” composed of these transactions. However, a directive-driven processor is required to execute each transaction in order to produce the desired address.