{"title":"110μW单比特连续时间ΔΣ转换器，动态范围92.5dB","authors":"S. Balagopal, Rajaram Mohan Roy, V. Saxena","doi":"10.1109/DCAS.2010.5955028","DOIUrl":null,"url":null,"abstract":"A third-order single-bit CT-ΔΣ modulator for generic biomedical applications is implemented in a 0.15-μm FD-SOI CMOS process. The overall power efficiency is attained by employing a single-bit quantizer and thus avoiding the mismatch shaping logic. The loop filter coefficients are determined using a systematic design centering approach by accounting for the integrator non-idealities. The single-bit CT-ΔΣ modulator consumes 110μW power from a 1.5-V power supply when clocked at 6.144MHz. The simulation results for the modulator exhibit a dynamic range of 94.4 dB and peak SNDR of 92.4 dB for 6 kHz signal bandwidth. The figure of merit (FoM) of this third-order, single-bit CT-ΔΣ modulator is 0.271pJ/level.","PeriodicalId":405694,"journal":{"name":"2010 IEEE Dallas Circuits and Systems Workshop","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 110μW single-bit continuous-time ΔΣ converter with 92.5dB dynamic range\",\"authors\":\"S. Balagopal, Rajaram Mohan Roy, V. Saxena\",\"doi\":\"10.1109/DCAS.2010.5955028\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A third-order single-bit CT-ΔΣ modulator for generic biomedical applications is implemented in a 0.15-μm FD-SOI CMOS process. The overall power efficiency is attained by employing a single-bit quantizer and thus avoiding the mismatch shaping logic. The loop filter coefficients are determined using a systematic design centering approach by accounting for the integrator non-idealities. The single-bit CT-ΔΣ modulator consumes 110μW power from a 1.5-V power supply when clocked at 6.144MHz. The simulation results for the modulator exhibit a dynamic range of 94.4 dB and peak SNDR of 92.4 dB for 6 kHz signal bandwidth. The figure of merit (FoM) of this third-order, single-bit CT-ΔΣ modulator is 0.271pJ/level.\",\"PeriodicalId\":405694,\"journal\":{\"name\":\"2010 IEEE Dallas Circuits and Systems Workshop\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 IEEE Dallas Circuits and Systems Workshop\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DCAS.2010.5955028\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE Dallas Circuits and Systems Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DCAS.2010.5955028","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 110μW single-bit continuous-time ΔΣ converter with 92.5dB dynamic range
A third-order single-bit CT-ΔΣ modulator for generic biomedical applications is implemented in a 0.15-μm FD-SOI CMOS process. The overall power efficiency is attained by employing a single-bit quantizer and thus avoiding the mismatch shaping logic. The loop filter coefficients are determined using a systematic design centering approach by accounting for the integrator non-idealities. The single-bit CT-ΔΣ modulator consumes 110μW power from a 1.5-V power supply when clocked at 6.144MHz. The simulation results for the modulator exhibit a dynamic range of 94.4 dB and peak SNDR of 92.4 dB for 6 kHz signal bandwidth. The figure of merit (FoM) of this third-order, single-bit CT-ΔΣ modulator is 0.271pJ/level.
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