Computational parameter study of chip scale package array cooling

This paper describes the results of a computational investigation into the thermal management of chip scale package arrays. The parameters considered include power dissipation, cooling air inlet velocity, chip package spacing, and circuit board conductivity. The geometry used throughout the study was an array of five packages placed on board with forced air cooling along the axis of the array. Each chip was the same size and dissipated the same amount of power. Free convection was included with gravity aligned normal to the plane of the circuit board. The effects of thermal radiation were neglected and the flow was considered to be laminar. Three dimensional solutions were generated using the commercial computational fluid dynamics code FLOTHERM. Results are presented in the form of thermal resistances for each package in the array. A number of interesting results were found. For the case of low conductivity circuit boards, the resistance for the first package in the array was a function of inlet velocity only. However, this was not the case when power planes were present and energy was conducted more effectively along the board. For low inlet velocities, when there are strong natural convection effects, there was a temperature overshoot such that the highest temperature does not occur in the last package of the array. Finally, when the effects of natural convection were small, the thermal resistance was relatively insensitive to the power dissipation.