S. Rathnam, G. Slavenburg, S. Nayak, E. Bellers, J. Janssen
{"title":"用于CRT和矩阵显示电视的单片混合媒体处理器","authors":"S. Rathnam, G. Slavenburg, S. Nayak, E. Bellers, J. Janssen","doi":"10.1109/ICCE.2003.1219001","DOIUrl":null,"url":null,"abstract":"The new generation of CRT or matrix displays-based television requires high quality video, audio and graphics processing at a lower cost. When available, such a media processing system will drive the wide spread usage of high performance television. A single chip hybrid (analog/digital) TV media processor is designed to implement high quality television at a lower cost.","PeriodicalId":319221,"journal":{"name":"2003 IEEE International Conference on Consumer Electronics, 2003. ICCE.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A single-chip hybrid media processor for CRT and matrix displays-based televisions\",\"authors\":\"S. Rathnam, G. Slavenburg, S. Nayak, E. Bellers, J. Janssen\",\"doi\":\"10.1109/ICCE.2003.1219001\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The new generation of CRT or matrix displays-based television requires high quality video, audio and graphics processing at a lower cost. When available, such a media processing system will drive the wide spread usage of high performance television. A single chip hybrid (analog/digital) TV media processor is designed to implement high quality television at a lower cost.\",\"PeriodicalId\":319221,\"journal\":{\"name\":\"2003 IEEE International Conference on Consumer Electronics, 2003. ICCE.\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-06-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2003 IEEE International Conference on Consumer Electronics, 2003. ICCE.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCE.2003.1219001\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2003 IEEE International Conference on Consumer Electronics, 2003. ICCE.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCE.2003.1219001","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A single-chip hybrid media processor for CRT and matrix displays-based televisions
The new generation of CRT or matrix displays-based television requires high quality video, audio and graphics processing at a lower cost. When available, such a media processing system will drive the wide spread usage of high performance television. A single chip hybrid (analog/digital) TV media processor is designed to implement high quality television at a lower cost.