H-tree CMOS逻辑电路

Shun-Wen Cheng
{"title":"H-tree CMOS逻辑电路","authors":"Shun-Wen Cheng","doi":"10.1109/ICECS.2008.4674910","DOIUrl":null,"url":null,"abstract":"Programmable routing networks and configurable logic blocks (CLB) achieve configurable computing of nowadays. This study proposed a novel H-tree configurable circuit. The 10-transistor (5P5N) CMOS version H-tree logic gate can generate AOI22, OAI22, AOI21, OAI21, NAND3, NAND2, NOR3, NOR2 and INV functions. A classic 8-to-1 multiplexer-based logic module needs 36 transistors to implement these functions; even an Actelpsilas ACT 1 logic module also needs 24 transistors to cover the job. Both the transistor count and layout cost of the proposed configurable gate are smaller than any other logic cell in FPGA/CPLD. The configurable logic gate could work with the existing logic cells to increase gate utilization and integration.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"221 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"H-tree CMOS logic circuit\",\"authors\":\"Shun-Wen Cheng\",\"doi\":\"10.1109/ICECS.2008.4674910\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Programmable routing networks and configurable logic blocks (CLB) achieve configurable computing of nowadays. This study proposed a novel H-tree configurable circuit. The 10-transistor (5P5N) CMOS version H-tree logic gate can generate AOI22, OAI22, AOI21, OAI21, NAND3, NAND2, NOR3, NOR2 and INV functions. A classic 8-to-1 multiplexer-based logic module needs 36 transistors to implement these functions; even an Actelpsilas ACT 1 logic module also needs 24 transistors to cover the job. Both the transistor count and layout cost of the proposed configurable gate are smaller than any other logic cell in FPGA/CPLD. The configurable logic gate could work with the existing logic cells to increase gate utilization and integration.\",\"PeriodicalId\":404629,\"journal\":{\"name\":\"2008 15th IEEE International Conference on Electronics, Circuits and Systems\",\"volume\":\"221 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-11-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 15th IEEE International Conference on Electronics, Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2008.4674910\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2008.4674910","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5

摘要

可编程路由网络和可配置逻辑块(CLB)实现了当今的可配置计算。本研究提出了一种新颖的h树可配置电路。10晶体管(5P5N) CMOS版h树逻辑门可生成AOI22、OAI22、AOI21、OAI21、NAND3、NAND2、NOR3、NOR2和INV功能。一个经典的基于8对1复用器的逻辑模块需要36个晶体管来实现这些功能;即使是Actelpsilas ACT 1逻辑模块也需要24个晶体管来完成这项工作。所提出的可配置门的晶体管数量和布局成本都小于FPGA/CPLD中任何其他逻辑单元。可配置逻辑门可与现有逻辑单元协同工作,提高了门的利用率和集成度。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
H-tree CMOS logic circuit
Programmable routing networks and configurable logic blocks (CLB) achieve configurable computing of nowadays. This study proposed a novel H-tree configurable circuit. The 10-transistor (5P5N) CMOS version H-tree logic gate can generate AOI22, OAI22, AOI21, OAI21, NAND3, NAND2, NOR3, NOR2 and INV functions. A classic 8-to-1 multiplexer-based logic module needs 36 transistors to implement these functions; even an Actelpsilas ACT 1 logic module also needs 24 transistors to cover the job. Both the transistor count and layout cost of the proposed configurable gate are smaller than any other logic cell in FPGA/CPLD. The configurable logic gate could work with the existing logic cells to increase gate utilization and integration.
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