{"title":"具有氧化物侧壁间隔的高性能横向DMOSFET","authors":"R. Fujishima, A. Kitamura, Y. Nagayasu","doi":"10.1109/ISPSD.1994.583768","DOIUrl":null,"url":null,"abstract":"A new lateral DMOSFET which utilizes oxide sidewall-spacers is described. The effective channel length is precisely controlled by the length of the spacer. The lateral DMOSFET with a channel length of 0.4 /spl mu/m shows a low channel resistance keeping high punch-through blocking capability. The process is compatible with the conventional 1 /spl mu/m Bi-CMOS process. The device characteristics are predicted by two-dimensional process and device simulators. Measurement results are also described. The developed DMOSFET shows an excellent specific on-resistance of 0.143 /spl Omega//spl middot/mm/sup 2/ and can withstand up to around 80 V.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":"35 5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"High-performance lateral DMOSFET with oxide sidewall-spacers\",\"authors\":\"R. Fujishima, A. Kitamura, Y. Nagayasu\",\"doi\":\"10.1109/ISPSD.1994.583768\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new lateral DMOSFET which utilizes oxide sidewall-spacers is described. The effective channel length is precisely controlled by the length of the spacer. The lateral DMOSFET with a channel length of 0.4 /spl mu/m shows a low channel resistance keeping high punch-through blocking capability. The process is compatible with the conventional 1 /spl mu/m Bi-CMOS process. The device characteristics are predicted by two-dimensional process and device simulators. Measurement results are also described. The developed DMOSFET shows an excellent specific on-resistance of 0.143 /spl Omega//spl middot/mm/sup 2/ and can withstand up to around 80 V.\",\"PeriodicalId\":405897,\"journal\":{\"name\":\"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics\",\"volume\":\"35 5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-05-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPSD.1994.583768\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.1994.583768","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High-performance lateral DMOSFET with oxide sidewall-spacers
A new lateral DMOSFET which utilizes oxide sidewall-spacers is described. The effective channel length is precisely controlled by the length of the spacer. The lateral DMOSFET with a channel length of 0.4 /spl mu/m shows a low channel resistance keeping high punch-through blocking capability. The process is compatible with the conventional 1 /spl mu/m Bi-CMOS process. The device characteristics are predicted by two-dimensional process and device simulators. Measurement results are also described. The developed DMOSFET shows an excellent specific on-resistance of 0.143 /spl Omega//spl middot/mm/sup 2/ and can withstand up to around 80 V.