{"title":"一种基于分散神经结构的二进制编码输出A/D转换器","authors":"M. Attari, F. Boudjema, M. Bouhedda, S. Bouallag","doi":"10.1109/IMTC.1997.603948","DOIUrl":null,"url":null,"abstract":"In this paper, a new approach is given to design a 4-bit decentralized flash analog to digital converter (ADC) with binary coded outputs. Four artificial neural networks (ANN) are chosen and trained to identify an ideal 4-bit ADC. In order to test the obtained neural ADC, simulation results are carried out to show the efficiency regarding to parallel encoders and neural ADCs already proposed.","PeriodicalId":124893,"journal":{"name":"IEEE Instrumentation and Measurement Technology Conference Sensing, Processing, Networking. IMTC Proceedings","volume":"150 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A decentralized neural architecture based A/D converter with binary coded outputs\",\"authors\":\"M. Attari, F. Boudjema, M. Bouhedda, S. Bouallag\",\"doi\":\"10.1109/IMTC.1997.603948\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a new approach is given to design a 4-bit decentralized flash analog to digital converter (ADC) with binary coded outputs. Four artificial neural networks (ANN) are chosen and trained to identify an ideal 4-bit ADC. In order to test the obtained neural ADC, simulation results are carried out to show the efficiency regarding to parallel encoders and neural ADCs already proposed.\",\"PeriodicalId\":124893,\"journal\":{\"name\":\"IEEE Instrumentation and Measurement Technology Conference Sensing, Processing, Networking. IMTC Proceedings\",\"volume\":\"150 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-05-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Instrumentation and Measurement Technology Conference Sensing, Processing, Networking. IMTC Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IMTC.1997.603948\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Instrumentation and Measurement Technology Conference Sensing, Processing, Networking. IMTC Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMTC.1997.603948","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A decentralized neural architecture based A/D converter with binary coded outputs
In this paper, a new approach is given to design a 4-bit decentralized flash analog to digital converter (ADC) with binary coded outputs. Four artificial neural networks (ANN) are chosen and trained to identify an ideal 4-bit ADC. In order to test the obtained neural ADC, simulation results are carried out to show the efficiency regarding to parallel encoders and neural ADCs already proposed.