{"title":"安全投机核心","authors":"A. Mendelson","doi":"10.1109/SOCC46988.2019.1570564192","DOIUrl":null,"url":null,"abstract":"The recent attacks on speculative cores have led people to believe that high-performance cores and security demands contradict each other. This work demonstrates that if the core is designed while considering security demands as a first-class citizen, it can support high-performance computing via out-of-order architectures and remain secure.We propose a new methodology for secure and speculative core (SCC) architecture. The design uses an enhanced out-of-order core architecture to achieve the required high-performance and implements a unique secure-wrapper that guarantees the required security properties. The methodology provides a set of mechanisms to implement the SSC architecture. Our experiments indicate that adding these new features to out-of-order cores such as the Intel Coffee Lake can immunize the system against side-channel attacks, with only minor performance degradation.","PeriodicalId":253998,"journal":{"name":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Secure Speculative Core\",\"authors\":\"A. Mendelson\",\"doi\":\"10.1109/SOCC46988.2019.1570564192\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The recent attacks on speculative cores have led people to believe that high-performance cores and security demands contradict each other. This work demonstrates that if the core is designed while considering security demands as a first-class citizen, it can support high-performance computing via out-of-order architectures and remain secure.We propose a new methodology for secure and speculative core (SCC) architecture. The design uses an enhanced out-of-order core architecture to achieve the required high-performance and implements a unique secure-wrapper that guarantees the required security properties. The methodology provides a set of mechanisms to implement the SSC architecture. Our experiments indicate that adding these new features to out-of-order cores such as the Intel Coffee Lake can immunize the system against side-channel attacks, with only minor performance degradation.\",\"PeriodicalId\":253998,\"journal\":{\"name\":\"2019 32nd IEEE International System-on-Chip Conference (SOCC)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 32nd IEEE International System-on-Chip Conference (SOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC46988.2019.1570564192\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 32nd IEEE International System-on-Chip Conference (SOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC46988.2019.1570564192","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The recent attacks on speculative cores have led people to believe that high-performance cores and security demands contradict each other. This work demonstrates that if the core is designed while considering security demands as a first-class citizen, it can support high-performance computing via out-of-order architectures and remain secure.We propose a new methodology for secure and speculative core (SCC) architecture. The design uses an enhanced out-of-order core architecture to achieve the required high-performance and implements a unique secure-wrapper that guarantees the required security properties. The methodology provides a set of mechanisms to implement the SSC architecture. Our experiments indicate that adding these new features to out-of-order cores such as the Intel Coffee Lake can immunize the system against side-channel attacks, with only minor performance degradation.