铁电三维nand中的变异性和干扰源以及与电荷阱等效物的比较

M. Pešić, A. Padovani, T. Rollo, Bastien Beltrando, J. Strand, Parnika Agrawal, A. Shluger, L. Larcher
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引用次数: 5

摘要

我们研究了驱动基于电荷阱(CT)和基于铁电(FE)的3D NAND串的保留和干扰的物理机制。结合校准后的CT 3D NAND模型和校准后的FE材料特性(从FE- finfet中提取),我们推断并比较了现有的主流产品与低功耗、高速的竞争者。我们发现:(1)固有的离散化fe稳定结合HZO的多晶性质和界面电荷补偿保证了MLC能力;(2) FE 3D NAND提供更高的ON电流,从而实现进一步的z缩放。此外,我们建立了一个保留模型,并表明,与存储层的继承离散无关,横向电荷迁移(寄生捕获的电荷稳定极化)结合通压(干扰)会导致FE 3D NAND的保留损失。最后,建议采用一体化(分层切割)和材料工程的方法来缓解和保证管柱的稳定运行。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Variability and disturb sources in ferroelectric 3D NANDs and comparison to Charge-Trap equivalents
We investigate physical mechanisms driving the retention and disturb of charge-trap (CT) based and ferroelectric-(FE) based 3D NAND string. Combining a calibrated CT 3D NAND model and calibrated material properties of the FE material (extracted from FE-FinFET), we extrapolate and compare the existing workhorse with the low-power, high-speed contender. We show that: (1) a inherently discretized FE-stabilization combined with the polycrystalline nature of HZO, and interface charge compensation guarantees MLC capability; (2) FE 3D NAND offers higher ON currents that enable further Z-scaling. Furthermore, we develop a retention model and show that independently of the inherited discretization of the storage layer, lateral charge migration (of the parasitically trapped charge that stabilizes polarization) combined with pass voltage (disturb) can cause retention loss of FE 3D NAND. Finally, integration (layer-cut) and material engineering approaches are suggested for mitigation and guaranteeing stable operation of the string.
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