基于标准差降噪的视差图像后处理的硬件设计与实现

Yongwoon Ji, Sang-Jun Lee, J. Jeon
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引用次数: 0

摘要

本文提出了一种基于标准差的视差后处理降噪方法,并给出了流水线专用硬件架构的设计与实现。在该方法中,首先利用迭代实验产生的参数计算最优标准差。通过这些参数,我们可以确定感兴趣的像素是否具有正确的视差值,并可以去除错误像素。我们在Xilinx Virtex5 FPGA上实现了所提出的专用硬件架构。该系统的平均工作频率高达80MHz,可实现60fps的实时流视频处理。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Hardware design and implementation of disparity image post-processing for noise reduction by standard deviation
This paper proposes a disparity post-processing method for noise reduction using standard deviation, and presents the design and implementation of pipelined dedicated hardware architecture for the real-time processing performance. In the proposed method, the optimal standard deviation is calculated first using the parameters generated by iterative experiments. Through these parameters, we can determine whether the pixel of interest has the correct disparity value and can remove error pixels. We implemented the proposed dedicated hardware architecture on a Xilinx Virtex5 FPGA. The average operating frequency of this system operated up to 80MHz, which enabled real-time streaming video processing at 60fps.
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