Dual Referencing Simulation Approach on High Speed Interconnects USB3.2 (10Gbps)

Despite our computing technology and platform design are trending toward higher speeds for better performance, on the contrary, the printed circuit board (PCB) form factor needs to scale smaller and thinner to allow for bigger battery for battery life improvement. Due to this, layout design with dual referenced (SIG-PWR or GND-SIG-PWR) stack-up could not be avoided at all due to the limitation that we have on routing spaces or routing layers. In this paper, signal and power integrity (SIPI) co-simulation approach on USB3.2 with dual referencing is described and discussed. The co-sim approach is carried out using Advanced Design System (ADS) tool in time-domain where the power noise is directly injected to the power plane and its noise coupling impact on USB3.2 eye opening at the receiver end is then observed.