T-depth Optimization for Fault-Tolerant Quantum Circuits

The $\mathrm{Clifford}+T$ gate library consisting of Hadamard, T, and CNOT gates has attracted much interest in quantum circuit synthesis, particularly due to its applicability to fault tolerant realizations. Since fault tolerant implementations of the $T$ gate have very high latency, recent work in this area is aiming at minimizing the number of $T$ stages, referred to as the T-depth. In this paper, we present an approach to exploit additional ancilla qubits in the mapping of reversible circuits consistina of multiple controlled Toffoli gates (MCT gates) into $\mathrm{califford}+T$ quantum circuits, with the primary optimization objective to minimize the $T$-depth. Our proposed approach takes advantage of and generalizes earlier work on corresponding mapping algorithms. An experimental evaluation shows that our approach leads to a significant $T$-depth reduction compared to earlier approaches.