利用广义极值分布统计估计纳米级互补金属氧化物半导体数字电路的泄漏功耗

H. Aghababa, A. Khosropour, A. Afzali-Kusha, B. Forouzandeh, Massoud Pedram
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引用次数: 8

摘要

在这项研究中,作者提出了一种准确的方法来估计纳米级互补金属氧化物半导体(CMOS)技术中存在工艺变化时泄漏功耗的统计分布。该技术是相对于个别栅极泄漏值的加法,采用广义极值(GEV)分布。与以往基于(双参数)对数正态分布的方法相比,该方法采用三参数的GEV分布,提高了精度。利用建议的分布,可以对电路的漏损率进行建模。通过将该方法的结果与先前技术的结果以及基于hspice的蒙特卡罗模拟在ISCAS85基准电路上的45 nm CMOS技术进行了比较,研究了该方法的准确性。比较表明,该方法具有较高的精度。与基于加性方法的对数正态分布相比,所提出的分布没有增加模拟的复杂性和成本。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Statistical estimation of leakage power dissipation in nano-scale complementary metal oxide semiconductor digital circuits using generalised extreme value distribution
In this study, the authors present an accurate approach for the estimation of statistical distribution of leakage power consumption in the presence of process variations in nano-scale complementary metal oxide semiconductor (CMOS) technologies. The technique, which is additive with respect to the individual gate leakage values, employs a generalised extreme value (GEV) distribution. Compared with the previous methods based on (two-parameter) lognormal distribution, this method uses the GEV distribution with three parameters to increase the accuracy. Using the suggested distribution, the leakage yield of the circuits may be modelled. The accuracy of the approach is studied by comparing its results with those of a previous technique and HSPICE-based Monte Carlo simulations on ISCAS85 benchmark circuits for 45 nm CMOS technology. The comparison reveals a higher accuracy for the proposed approach. The proposed distribution does not add to the complexity and cost of simulations compared with the case of the lognormal distribution based on the additive approach.
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