D. Kenney, P. Parries, P. Pan, W. Tonti, W. Cote, S. Dash, P. Lorenz, W. Arden, R. Mohler, S. Roehl, A. Bryant, W. Haensch, B. Hoffmann, M. Levy, A. Yu, C. Zeller
{"title":"用于64兆DRAM的埋板槽电池","authors":"D. Kenney, P. Parries, P. Pan, W. Tonti, W. Cote, S. Dash, P. Lorenz, W. Arden, R. Mohler, S. Roehl, A. Bryant, W. Haensch, B. Hoffmann, M. Levy, A. Yu, C. Zeller","doi":"10.1109/VLSIT.1992.200620","DOIUrl":null,"url":null,"abstract":"A technology for fabricating a 64-Mb DRAM is described. The basic cell concept is an evolution from IBM's SPT cell and a modified SPT cell. Ground-rule shrinkage and additional features permit the realization of a cell size of 1.5 mu m/sup 2/. The chip incorporates N-array transfer gates isolated from the P-substrate by an intervening buried N-layer which forms the buried plate for the trench capacitor. The N-array devices, isolated P-well, and low-resistance wordline conductors provide a dense cell with superior soft-error-rate (SER) protection. Density improvement is achieved by the use of fully borderless contacts and ground-rule shrinkage. The interconnects use a Damascene metallization scheme that repeatedly applies chemical-mechanical polishes for dielectrics and metals.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"545 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A buried-plate trench cell for a 64-Mb DRAM\",\"authors\":\"D. Kenney, P. Parries, P. Pan, W. Tonti, W. Cote, S. Dash, P. Lorenz, W. Arden, R. Mohler, S. Roehl, A. Bryant, W. Haensch, B. Hoffmann, M. Levy, A. Yu, C. Zeller\",\"doi\":\"10.1109/VLSIT.1992.200620\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A technology for fabricating a 64-Mb DRAM is described. The basic cell concept is an evolution from IBM's SPT cell and a modified SPT cell. Ground-rule shrinkage and additional features permit the realization of a cell size of 1.5 mu m/sup 2/. The chip incorporates N-array transfer gates isolated from the P-substrate by an intervening buried N-layer which forms the buried plate for the trench capacitor. The N-array devices, isolated P-well, and low-resistance wordline conductors provide a dense cell with superior soft-error-rate (SER) protection. Density improvement is achieved by the use of fully borderless contacts and ground-rule shrinkage. The interconnects use a Damascene metallization scheme that repeatedly applies chemical-mechanical polishes for dielectrics and metals.<<ETX>>\",\"PeriodicalId\":404756,\"journal\":{\"name\":\"1992 Symposium on VLSI Technology Digest of Technical Papers\",\"volume\":\"545 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-06-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1992 Symposium on VLSI Technology Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1992.200620\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1992 Symposium on VLSI Technology Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1992.200620","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A technology for fabricating a 64-Mb DRAM is described. The basic cell concept is an evolution from IBM's SPT cell and a modified SPT cell. Ground-rule shrinkage and additional features permit the realization of a cell size of 1.5 mu m/sup 2/. The chip incorporates N-array transfer gates isolated from the P-substrate by an intervening buried N-layer which forms the buried plate for the trench capacitor. The N-array devices, isolated P-well, and low-resistance wordline conductors provide a dense cell with superior soft-error-rate (SER) protection. Density improvement is achieved by the use of fully borderless contacts and ground-rule shrinkage. The interconnects use a Damascene metallization scheme that repeatedly applies chemical-mechanical polishes for dielectrics and metals.<>
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