非状态动态排水应力评估集成测试电路

2023 IEEE International Reliability Physics Symposium (IRPS) Pub Date : 2023-03-01 DOI:10.1109/IRPS48203.2023.10117885

J. Hai, F. Cacho, X. Federspiel, T. Garba-Seybou, A. Divay, E. Lauga-Larroze, J. Arnould

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引用次数: 0

摘要

通过集成测试电路研究射频应用的动态非状态应力，以实现GHz级测试。我们对测试电路进行了表征，以确保动态应力信号波形的完整性，并通过模型仿真数据进行了验证。我们报告在1GHz下对直流TDDB非状态应力的击穿时间增益为x2。基于$\boldsymbol{\ maththrm {I}_{\text{Dlin}}}$退化的提取，从直流到1GHz的非状态应力条件下，没有观察到频率效应。基于退化模式总和的状态和非状态相互作用的建模随后得到了实验数据的证明和支持。

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Integrated Test Circuit for Off-State Dynamic Drain Stress Evaluation

Dynamic off-state stress for RF applications is investigated via integrated test circuits to enable GHz level testing. We have performed characterization of test circuits to ensure the dynamic stress signal waveform integrity, which is verified against model simulation data. We report a x2 gain on time-to-breakdown at 1GHz against DC TDDB off-state stress. Based on extraction of $\boldsymbol{\mathrm{I}_{\text{Dlin}}}$ degradation, no frequency effect is observed from DC to 1GHz off-state stress conditions. Modeling of on-state and off-state interactions based on sum of degradations modes is then demonstrated and supported by experimental data.

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2023 IEEE International Reliability Physics Symposium (IRPS)

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