Design of Low Voltage-Power: Negative capacitance Charge Plasma FinTFET for AIOT Data Acquisition Blocks

The advancement of technological improvement are revved up to introduce the notion of Artificial Intelligence of Things (AIOT) to eliminate human interaction in operation of the machine and thus improve data throughput and big data potential. Lower voltage-power operation and higher performance are the goals of AIOT hardware design. As a result, future AIOT hardware devices will focus on the fabrication of rad-hard and steeper slope transistors, as well as high drive on-state and low ambipolar currents. These design features will help AIOT apps become more sophisticated. Tunnel FETs are the most effective at reducing leakage current, but the equivalent current must be increased. To ensure high drive and low leakage currents, this work incorporates both negative capacitance and charged plasma principles into the Tunnel FET design. The goal of this research is to construct a Negative Capacitance Charge Plasma Fin Gate TFET, and Centaurs TCAD simulations are used to examine the properties. As a result, the perspective model potentially achieve a subthreshold swing of less than 20 mV/decade and a switching voltage of less than 0.2 V, as well as the highest on current and lowest ambipolar leakage current. Using the suggested devices to implement current mirror and cascade current mirror circuits can lead to the most efficient, tolerant, and minor circuits with adjustable properties, which are critical for the intend of low-power and high-speed data collecting systems in AIOT applications.