Methods for Fast Characterization of Noise and Offset in Dynamic Comparators

The dynamic comparator is the core building block of most architectures of analog-to-digital converters (ADCs). Comparator noise and offset have critical impact on overall ADC performance, thus requiring a careful comparator characterization routine. Due to the dynamic nature of such circuits, the performance assessment becomes a challenging task when relying on conventional simulation-based analysis. In this paper two alternative approaches to simulate dynamic comparator noise and offset are discussed. By relying on periodic steady-state (PSS), periodic transfer function (PXF) and periodic noise (PNOISE) analyses the noise of a dynamic comparator can be obtained in a fraction of the time when compared to traditional transient noise simulations. A binary-search-based Verilog-A Offset Tester block is also presented as a mean to speed-up the offset characterization. The PSS + PXF + PNOISE method achieves a 220× decrease in simulation time, while the Verilog-A Offset Tester allows a 60× simulation time reduction.