{"title":"片上I/O电源噪声测量及单点登录引起的噪声幅度与时延增加的相关性验证","authors":"Y. Takai, Y. Ogasahara, M. Hashimoto, T. Onoye","doi":"10.1109/SPI.2010.5483591","DOIUrl":null,"url":null,"abstract":"This paper presents measurement results of on-chip noise on power and ground rings for I/O (input/output) cells in a simple test structure fabricated in 90nm process. We also show measured timings of an output signal from chip to PCB board, and examine the relation between the magnitude of I/O power supply noise and the output transition timings.","PeriodicalId":293987,"journal":{"name":"2010 IEEE 14th Workshop on Signal Propagation on Interconnects","volume":"214 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Measurement of on-chip I/O power supply noise and correlation verification between noise magnitude and delay increase due to SSO\",\"authors\":\"Y. Takai, Y. Ogasahara, M. Hashimoto, T. Onoye\",\"doi\":\"10.1109/SPI.2010.5483591\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents measurement results of on-chip noise on power and ground rings for I/O (input/output) cells in a simple test structure fabricated in 90nm process. We also show measured timings of an output signal from chip to PCB board, and examine the relation between the magnitude of I/O power supply noise and the output transition timings.\",\"PeriodicalId\":293987,\"journal\":{\"name\":\"2010 IEEE 14th Workshop on Signal Propagation on Interconnects\",\"volume\":\"214 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-05-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 IEEE 14th Workshop on Signal Propagation on Interconnects\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SPI.2010.5483591\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE 14th Workshop on Signal Propagation on Interconnects","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPI.2010.5483591","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Measurement of on-chip I/O power supply noise and correlation verification between noise magnitude and delay increase due to SSO
This paper presents measurement results of on-chip noise on power and ground rings for I/O (input/output) cells in a simple test structure fabricated in 90nm process. We also show measured timings of an output signal from chip to PCB board, and examine the relation between the magnitude of I/O power supply noise and the output transition timings.