{"title":"用于电路仿真的多晶硅TFT模型","authors":"X. Guan, Xiaoyan Liu, R. Han","doi":"10.1109/ICSICT.1995.503365","DOIUrl":null,"url":null,"abstract":"This paper presents a polysilicon thin film transistor (TFT) model for circuit simulation. In this model, the effects of grain boundaries on the turn-on behavior of polysilicon TFT is considered. The potential barrier height is expressed in terms of channel doping, gate oxide thickness, grain size and external gate biases. Based on this, the analytical I-V characteristics are obtained for circuit simulation. Comparisons between the model and the experimental data have been made.","PeriodicalId":286176,"journal":{"name":"Proceedings of 4th International Conference on Solid-State and IC Technology","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A poly-silicon TFT model for circuit simulation\",\"authors\":\"X. Guan, Xiaoyan Liu, R. Han\",\"doi\":\"10.1109/ICSICT.1995.503365\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a polysilicon thin film transistor (TFT) model for circuit simulation. In this model, the effects of grain boundaries on the turn-on behavior of polysilicon TFT is considered. The potential barrier height is expressed in terms of channel doping, gate oxide thickness, grain size and external gate biases. Based on this, the analytical I-V characteristics are obtained for circuit simulation. Comparisons between the model and the experimental data have been made.\",\"PeriodicalId\":286176,\"journal\":{\"name\":\"Proceedings of 4th International Conference on Solid-State and IC Technology\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 4th International Conference on Solid-State and IC Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSICT.1995.503365\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 4th International Conference on Solid-State and IC Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT.1995.503365","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents a polysilicon thin film transistor (TFT) model for circuit simulation. In this model, the effects of grain boundaries on the turn-on behavior of polysilicon TFT is considered. The potential barrier height is expressed in terms of channel doping, gate oxide thickness, grain size and external gate biases. Based on this, the analytical I-V characteristics are obtained for circuit simulation. Comparisons between the model and the experimental data have been made.
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