包装互连对包装设计的影响

2007 IEEE Workshop on Signal Propagation on Interconnects Pub Date : 2007-05-13 DOI:10.1109/SPI.2007.4512239

P. Pulici, G. Candela, G. Campardo, G. Vanalli, P. Stoppino, A. Losavio, T. Lessio, M. Dellutri, D. Guarnaccia, F. Lo Iacono

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引用次数: 5

摘要

本文描述了PoP (Package on Package)设计过程，主要侧重于约束条件和系统特性。PoP结构越来越普及，因为它通过对顶部和底部设备进行单独测试来增加客户的灵活性和最终成品率。本文描述了一种由两个堆叠存储器(NOR闪存和SDRAM)组成的Top PoP设计，指出了电气封装的影响。内存PoP的访问速度必须达到250 Mb/s。这样的频率涉及到要根据一些规则设计的封装，并通过信号完整性流来评估其电气影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Interconnection effects in Package on Package design

The PoP (Package on Package) design procedure is described in this paper, focusing principally on the constraints and the system characteristics. The PoP structure is more and more diffused because it increases the customer flexibility and the final yield by means of a separate testing of Top and Bottom devices. In this paper, a Top PoP design, composed by two stacked memory dice (a NOR Flash and a SDRAM), is described pointing out the electrical package impact. The memory PoP has to be accessed up to 250 Mb/s. Such a frequency involves the package to be designed basing on some rules and evaluating its electrical impact by means of a signal integrity flow.

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2007 IEEE Workshop on Signal Propagation on Interconnects

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