{"title":"基于FPGA的非线性函数生成自适应神经模糊推理系统的设计与实现","authors":"H. J. B. Saldana, C. S. Cárdenas","doi":"10.1109/ANDESCON.2010.5633065","DOIUrl":null,"url":null,"abstract":"This paper presents a digital system architecture for a two-input one-output zero order ANFIS (Adaptive Neuro-Fuzzy Inference System) and its implementation on an FPGA (Field Programmable Gate Array) using VHDL (VHSIC Hardware Description Language). The designed system is used for nonlinear function generation. First, a nonlinear function is chosen and off-line training is carried out using MATLAB ANFIS to obtain the premise and consequence parameters of the fuzzy rules. Then, these parameters are converted to a binary fixed-point representation and are stored in read-only memories of the VHDL code. Finally, simulations are performed to verify the system operation and to evaluate the system response time for given input data.","PeriodicalId":359559,"journal":{"name":"2010 IEEE ANDESCON","volume":"125 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"Design and implementation of an adaptive neuro-fuzzy inference system on an FPGA used for nonlinear function generation\",\"authors\":\"H. J. B. Saldana, C. S. Cárdenas\",\"doi\":\"10.1109/ANDESCON.2010.5633065\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a digital system architecture for a two-input one-output zero order ANFIS (Adaptive Neuro-Fuzzy Inference System) and its implementation on an FPGA (Field Programmable Gate Array) using VHDL (VHSIC Hardware Description Language). The designed system is used for nonlinear function generation. First, a nonlinear function is chosen and off-line training is carried out using MATLAB ANFIS to obtain the premise and consequence parameters of the fuzzy rules. Then, these parameters are converted to a binary fixed-point representation and are stored in read-only memories of the VHDL code. Finally, simulations are performed to verify the system operation and to evaluate the system response time for given input data.\",\"PeriodicalId\":359559,\"journal\":{\"name\":\"2010 IEEE ANDESCON\",\"volume\":\"125 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-11-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 IEEE ANDESCON\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ANDESCON.2010.5633065\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE ANDESCON","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ANDESCON.2010.5633065","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design and implementation of an adaptive neuro-fuzzy inference system on an FPGA used for nonlinear function generation
This paper presents a digital system architecture for a two-input one-output zero order ANFIS (Adaptive Neuro-Fuzzy Inference System) and its implementation on an FPGA (Field Programmable Gate Array) using VHDL (VHSIC Hardware Description Language). The designed system is used for nonlinear function generation. First, a nonlinear function is chosen and off-line training is carried out using MATLAB ANFIS to obtain the premise and consequence parameters of the fuzzy rules. Then, these parameters are converted to a binary fixed-point representation and are stored in read-only memories of the VHDL code. Finally, simulations are performed to verify the system operation and to evaluate the system response time for given input data.