改进的功率约束同时噪声和输入匹配2.45 GHz CMOS NB-LNA

2012 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2012-10-01 DOI:10.1109/ICCIRCUITSANDSYSTEMS.2012.6408341

H. A. Eshghabadi, F. Eshghabadi, M. T. Mustaffa, N. Noh, A. A. Manaf, O. Sidek

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引用次数: 9

摘要

本文提出了一种优化工作在2.45 GHz中心频率的全集成两级窄带低噪声放大器。采用基于功率约束同步噪声和输入匹配(PCSNIM)技术的感应源退化级联码拓扑结构，使LNA适用于基于0.13 μm Silterra CMOS技术的低功耗应用。后布局仿真结果表明，在1.2 V电源电压下消耗4 mA直流电流时，功率增益为22 dB, NF为2.06 dB, S11为-19 dB, S22为-12 dB。

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An improved power constrained simultaneous noise and input matched 2.45 GHz CMOS NB-LNA

This paper presents a fully integrated two-stage narrow-band low noise amplifier which optimized to work in 2.45 GHz center frequency. The topology of inductive source degenerated cascode based on power-constrained simultaneous noise and input matching (PCSNIM) technique has been adopted to make the LNA suitable for low power applications based on 0.13 μm Silterra CMOS technology. Post layout simulation results show power gain of 22 dB, NF of 2.06 dB, S11 of -19 dB and S22 of -12 dB while consuming the DC current of 4 mA at supply voltage of 1.2 V.

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2012 IEEE International Conference on Circuits and Systems (ICCAS)

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