开发各种软ip的高效系统

Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI:10.1109/APASIC.2000.896951

J. Bae, Seong-Jun Kyung, M. Ahn, Seong-Sik Kim, Ji-Soo Lim, Wook-Jin Cha, Jong-Oh Lee, H. Kwon, Se-Jin Yoo, Dong-Soo Cho, Jay S. Chae

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引用次数: 0

摘要

超大规模集成电路技术的不断发展使得复杂的系统可以集成在一个芯片上。设计一个大复杂度的系统，最好是设计好的宏块，即IP (Intellectual Property)，这样可以大大减少设计时间。开发了一种名为ART(自动RTL翻译)的系统，用于从遗留硬宏生成可合成的RTL ip。借助ART系统，我们开发了一个8位嵌入式微控制器的软IP。IP的工作频率高达80mhz，采用0.6 /spl mu/m CMOS技术。利用该IP技术开发了数字调谐系统(DTS)的单片机。

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An efficient system to develop various soft IPs

Evolutional enhancement in VLSI technology makes a complicated system integrated in a chip. To design a system with large complexity, well-designed macro block, IP (Intellectual Property), is preferred to reduce design time enormously. A system, named ART (automatic RTL translation), is developed to generate synthesizable RTL IPs from legacy hard macros. With help of the ART system, we developed a soft IP of an 8-bit embedded microcontroller. The operating frequency of the IP is up to 80 MHz with a 0.6 /spl mu/m CMOS technology. An MCU for Digital Tuning System (DTS) was also developed using the IP with the same technology.

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Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)

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