{"title":"基于SiGe BiCMOS技术实现的40gbps微环调制器驱动","authors":"A. Fatemi, H. Klar, F. Gerfers, D. Kissinger","doi":"10.1109/CSICS.2016.7751016","DOIUrl":null,"url":null,"abstract":"This paper presents a 40 Gbps micro-ring modulator driver IC implemented in a 130nm SiGe BiCMOS technology providing a fT,max of 250GHz. The proposed bandwidth-optimized driver IC achieves 2Vppd output signal swing required for the integrated high-impedance silicon photonics ring modulator or 1Vppd when differentially terminated with 100Ω. The complete driver including input termination and biasing consumes 90mW operated from a single 2:5V power supply. The inductor-less driver architecture exploits a current density optimized cascode topology with capacitive degeneration to improve both, the overall bandwidth and the output voltage swing. The driver core occupies only 0.04mm2. Small-signal measurements show a differential gain of 16dB with a -3dB bandwidth of 33GHz and a return loss of -15dB at 33GHz. This design represents one of the fastest micro-ring modulator drivers with FOM of 2.25 pJ/(bit×⌉Vppd) above 25 Gbps.","PeriodicalId":183218,"journal":{"name":"2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 40 Gbps Micro-Ring Modulator Driver Implemented in a SiGe BiCMOS Technology\",\"authors\":\"A. Fatemi, H. Klar, F. Gerfers, D. Kissinger\",\"doi\":\"10.1109/CSICS.2016.7751016\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a 40 Gbps micro-ring modulator driver IC implemented in a 130nm SiGe BiCMOS technology providing a fT,max of 250GHz. The proposed bandwidth-optimized driver IC achieves 2Vppd output signal swing required for the integrated high-impedance silicon photonics ring modulator or 1Vppd when differentially terminated with 100Ω. The complete driver including input termination and biasing consumes 90mW operated from a single 2:5V power supply. The inductor-less driver architecture exploits a current density optimized cascode topology with capacitive degeneration to improve both, the overall bandwidth and the output voltage swing. The driver core occupies only 0.04mm2. Small-signal measurements show a differential gain of 16dB with a -3dB bandwidth of 33GHz and a return loss of -15dB at 33GHz. This design represents one of the fastest micro-ring modulator drivers with FOM of 2.25 pJ/(bit×⌉Vppd) above 25 Gbps.\",\"PeriodicalId\":183218,\"journal\":{\"name\":\"2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)\",\"volume\":\"109 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CSICS.2016.7751016\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSICS.2016.7751016","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 40 Gbps Micro-Ring Modulator Driver Implemented in a SiGe BiCMOS Technology
This paper presents a 40 Gbps micro-ring modulator driver IC implemented in a 130nm SiGe BiCMOS technology providing a fT,max of 250GHz. The proposed bandwidth-optimized driver IC achieves 2Vppd output signal swing required for the integrated high-impedance silicon photonics ring modulator or 1Vppd when differentially terminated with 100Ω. The complete driver including input termination and biasing consumes 90mW operated from a single 2:5V power supply. The inductor-less driver architecture exploits a current density optimized cascode topology with capacitive degeneration to improve both, the overall bandwidth and the output voltage swing. The driver core occupies only 0.04mm2. Small-signal measurements show a differential gain of 16dB with a -3dB bandwidth of 33GHz and a return loss of -15dB at 33GHz. This design represents one of the fastest micro-ring modulator drivers with FOM of 2.25 pJ/(bit×⌉Vppd) above 25 Gbps.