Staffan Ek, Patrik Karlsson, Andreas Kämpe, R. Strandberg, A. Narayanan, Martin Anderson, Hind Dafallah, Mesrop Daghbashyan, Tayebeh Ghanavati Nejad, Robert Hägglund, N. Ivanisevic, R. Nilsson, Peter Nygren, Mattias Palm, Erik Säll, S. Tao, My-Chien Yee, Lars Sundström
{"title":"一个覆盖11.1-14.3 GHz和14.7-18.7 GHz的Bang-Bang数字锁相环，在7nm FinFET技术中RMS抖动低于40fs","authors":"Staffan Ek, Patrik Karlsson, Andreas Kämpe, R. Strandberg, A. Narayanan, Martin Anderson, Hind Dafallah, Mesrop Daghbashyan, Tayebeh Ghanavati Nejad, Robert Hägglund, N. Ivanisevic, R. Nilsson, Peter Nygren, Mattias Palm, Erik Säll, S. Tao, My-Chien Yee, Lars Sundström","doi":"10.1109/ESSCIRC55480.2022.9911298","DOIUrl":null,"url":null,"abstract":"This paper presents an integer-N bang-bang digital PLL for synthesis of a high purity clock targeting output frequencies of 12 and 16 GHz using a 500 MHz reference. The PLL uses a self-resetting differential comparator-based BBPD with low hysteresis and a dual DCO architecture for lowest phase noise at respective output frequency. The PLL is implemented in a 7 nm FinFET process with an area of 0.18 mm2and achieves <40fs RMS jitter integrated between 1 kHz and 100MHz with a phase noise of -118.6 dBc/Hz at 1 MHz offset, while consuming 85.4 mW. The jitter varies less than 1.5dB across a -40 C to +85 C ambient temperature range.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A Bang-Bang Digital PLL Covering 11.1-14.3 GHz and 14.7-18.7 GHz with sub-40 fs RMS Jitter in 7 nm FinFET Technology\",\"authors\":\"Staffan Ek, Patrik Karlsson, Andreas Kämpe, R. Strandberg, A. Narayanan, Martin Anderson, Hind Dafallah, Mesrop Daghbashyan, Tayebeh Ghanavati Nejad, Robert Hägglund, N. Ivanisevic, R. Nilsson, Peter Nygren, Mattias Palm, Erik Säll, S. Tao, My-Chien Yee, Lars Sundström\",\"doi\":\"10.1109/ESSCIRC55480.2022.9911298\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an integer-N bang-bang digital PLL for synthesis of a high purity clock targeting output frequencies of 12 and 16 GHz using a 500 MHz reference. The PLL uses a self-resetting differential comparator-based BBPD with low hysteresis and a dual DCO architecture for lowest phase noise at respective output frequency. The PLL is implemented in a 7 nm FinFET process with an area of 0.18 mm2and achieves <40fs RMS jitter integrated between 1 kHz and 100MHz with a phase noise of -118.6 dBc/Hz at 1 MHz offset, while consuming 85.4 mW. The jitter varies less than 1.5dB across a -40 C to +85 C ambient temperature range.\",\"PeriodicalId\":168466,\"journal\":{\"name\":\"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-09-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC55480.2022.9911298\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC55480.2022.9911298","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Bang-Bang Digital PLL Covering 11.1-14.3 GHz and 14.7-18.7 GHz with sub-40 fs RMS Jitter in 7 nm FinFET Technology
This paper presents an integer-N bang-bang digital PLL for synthesis of a high purity clock targeting output frequencies of 12 and 16 GHz using a 500 MHz reference. The PLL uses a self-resetting differential comparator-based BBPD with low hysteresis and a dual DCO architecture for lowest phase noise at respective output frequency. The PLL is implemented in a 7 nm FinFET process with an area of 0.18 mm2and achieves <40fs RMS jitter integrated between 1 kHz and 100MHz with a phase noise of -118.6 dBc/Hz at 1 MHz offset, while consuming 85.4 mW. The jitter varies less than 1.5dB across a -40 C to +85 C ambient temperature range.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
