M. Nakayama, K. Mori, N. Ogata, Y. Mitsui, H. Yuura, Y. Yoshii, K. Yamamoto, K. Maemura, O. Ishida
{"title":"用于个人通信的1.9 GHz单芯片射频前端GaAs MMIC","authors":"M. Nakayama, K. Mori, N. Ogata, Y. Mitsui, H. Yuura, Y. Yoshii, K. Yamamoto, K. Maemura, O. Ishida","doi":"10.1109/MCS.1996.506305","DOIUrl":null,"url":null,"abstract":"A single-chip RF front-end GaAs MMIC for the 1.9 GHz Japanese Personal Handy-phone System (PHS) is presented. RF circuits of a high power amplifier (HPA), a T/R switch (SW), two attenuators (ATTs), and a low-noise amplifier (LNA), are integrated with digital circuits of a negative voltage generator (NVG) for HPA and SW gate bias and a logic circuit to control the RF circuits. The HPA has an output power of 21.5 dBm and a high efficiency of 35% with sufficient linearity. The T/R SW combined with a receive step-ATT (0/20 dB) has loss of 1.2 dB (include the ATT loss). The LNA has a gain of 11 dB with noise figure of 1.7 dB, which is self-biased to a steep negative voltage generator during the receive mode. The IC needs only a single voltage (+3 V) DC power supply, and has a logic interface to control each mode for the TDMA/TDD scheme.","PeriodicalId":227834,"journal":{"name":"IEEE 1996 Microwave and Millimeter-Wave Monolithic Circuits Symposium. Digest of Papers","volume":"64 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A 1.9 GHz single-chip RF front-end GaAs MMIC for personal communications\",\"authors\":\"M. Nakayama, K. Mori, N. Ogata, Y. Mitsui, H. Yuura, Y. Yoshii, K. Yamamoto, K. Maemura, O. Ishida\",\"doi\":\"10.1109/MCS.1996.506305\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A single-chip RF front-end GaAs MMIC for the 1.9 GHz Japanese Personal Handy-phone System (PHS) is presented. RF circuits of a high power amplifier (HPA), a T/R switch (SW), two attenuators (ATTs), and a low-noise amplifier (LNA), are integrated with digital circuits of a negative voltage generator (NVG) for HPA and SW gate bias and a logic circuit to control the RF circuits. The HPA has an output power of 21.5 dBm and a high efficiency of 35% with sufficient linearity. The T/R SW combined with a receive step-ATT (0/20 dB) has loss of 1.2 dB (include the ATT loss). The LNA has a gain of 11 dB with noise figure of 1.7 dB, which is self-biased to a steep negative voltage generator during the receive mode. The IC needs only a single voltage (+3 V) DC power supply, and has a logic interface to control each mode for the TDMA/TDD scheme.\",\"PeriodicalId\":227834,\"journal\":{\"name\":\"IEEE 1996 Microwave and Millimeter-Wave Monolithic Circuits Symposium. Digest of Papers\",\"volume\":\"64 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-06-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE 1996 Microwave and Millimeter-Wave Monolithic Circuits Symposium. Digest of Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MCS.1996.506305\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE 1996 Microwave and Millimeter-Wave Monolithic Circuits Symposium. Digest of Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MCS.1996.506305","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1.9 GHz single-chip RF front-end GaAs MMIC for personal communications
A single-chip RF front-end GaAs MMIC for the 1.9 GHz Japanese Personal Handy-phone System (PHS) is presented. RF circuits of a high power amplifier (HPA), a T/R switch (SW), two attenuators (ATTs), and a low-noise amplifier (LNA), are integrated with digital circuits of a negative voltage generator (NVG) for HPA and SW gate bias and a logic circuit to control the RF circuits. The HPA has an output power of 21.5 dBm and a high efficiency of 35% with sufficient linearity. The T/R SW combined with a receive step-ATT (0/20 dB) has loss of 1.2 dB (include the ATT loss). The LNA has a gain of 11 dB with noise figure of 1.7 dB, which is self-biased to a steep negative voltage generator during the receive mode. The IC needs only a single voltage (+3 V) DC power supply, and has a logic interface to control each mode for the TDMA/TDD scheme.