{"title":"数字VLSI实现的一种神经处理器","authors":"F. Castillo, J. Moreno, J. Cabestany","doi":"10.1109/MELCON.1991.161838","DOIUrl":null,"url":null,"abstract":"The design of a digital neural processor based on a VLSI architecture is discussed. Each processor is an element of a systolic array capable of performing the backpropagation algorithm. The processor's internal structure and its characteristics are discussed.<<ETX>>","PeriodicalId":193917,"journal":{"name":"[1991 Proceedings] 6th Mediterranean Electrotechnical Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Digital VLSI implementation of a neural processor\",\"authors\":\"F. Castillo, J. Moreno, J. Cabestany\",\"doi\":\"10.1109/MELCON.1991.161838\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The design of a digital neural processor based on a VLSI architecture is discussed. Each processor is an element of a systolic array capable of performing the backpropagation algorithm. The processor's internal structure and its characteristics are discussed.<<ETX>>\",\"PeriodicalId\":193917,\"journal\":{\"name\":\"[1991 Proceedings] 6th Mediterranean Electrotechnical Conference\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-05-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1991 Proceedings] 6th Mediterranean Electrotechnical Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MELCON.1991.161838\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991 Proceedings] 6th Mediterranean Electrotechnical Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MELCON.1991.161838","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The design of a digital neural processor based on a VLSI architecture is discussed. Each processor is an element of a systolic array capable of performing the backpropagation algorithm. The processor's internal structure and its characteristics are discussed.<>
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