Performance of Gigabit Atm Switch Designs

In this presentation, we discuss performance issues (delay, throughput, and cell loss) associated with gigabit-per-second ATM switch designs. Much of our attention focuses on the issue of hierarchical multiplexing in ATM switch design. As with circuit switches, the interface 1 data rates to the external lines (i.e., line card data rates) can be and usually are different from the internal core fabric speed of an ATM switch. To avoid a large delay penalty for the high speed interfaces, the internal core fabric speed needs to be at least as large as the maximum interface data rate. If the switch first demultiplexed a high-speed signal to multiple inputs of a "low-speed core fabric (e.g., demultiplexed a 2.4-Cb/s signal to sixteen 150-Mb/s input lines), then the delay would be quite large (compared to using a 2.4-Gb/s core fabric) [1].