Fast and generic hardware architecture for stereo block matching applications on embedded systems

Even with the tremendous performance increase of microprocessor architectures in recent years, real time capturing and computing of stereo images remains a challenging task, particularly in the field of embedded image processing. The stereo block matching technique allows hardware designers to parallelize the process of depth map calculation. Additionally, for smart camera designers it is also crucial to adapt hardware architectures for different FPGA platforms, sensor properties, throughput, and accuracy. However, most application specific implementations of this technique are usually fixed to a single camera set up to achieve high frame rates, but lack in flexibility of these properties. A general approach for a stereo block matching model, which is also able to process high resolution images in real time, is still missing. Therefore, we present a new generic VHDL template for fast window based stereo block matching correlation. It is fully scalable in functional parameters like image size, window size, and disparity range. Its streaming character even allows to compute HD images in real time. Also an interface for a flexible PE structure is provided. This enables the hardware designer to apply a custom made cost function, which performs a correlation between the target windows and the reference window. The developer is also able to adapt the model to the available sensor speed and FPGA resource limitations. These features should help designers to find the right trade-off between depth map quality and available hardware resources.