组合电路的测试装置压实

Proceedings First Asian Test Symposium (ATS `92) Pub Date : 1992-11-26 DOI:10.1109/ATS.1992.224429

Jau-Shien Chang, Chen-Shang Lin

{"title":"组合电路的测试装置压实","authors":"Jau-Shien Chang, Chen-Shang Lin","doi":"10.1109/ATS.1992.224429","DOIUrl":null,"url":null,"abstract":"Test set compaction for combinational circuits is studied. Two active compaction methods, forced pair-merging and essential fault pruning, are developed to reduce a given test set. Together these two methods, the compacted test size is smaller than known best results by more than 20% and is only 20% larger than the established lower bound.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"145","resultStr":"{\"title\":\"Test set compaction for combinational circuits\",\"authors\":\"Jau-Shien Chang, Chen-Shang Lin\",\"doi\":\"10.1109/ATS.1992.224429\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Test set compaction for combinational circuits is studied. Two active compaction methods, forced pair-merging and essential fault pruning, are developed to reduce a given test set. Together these two methods, the compacted test size is smaller than known best results by more than 20% and is only 20% larger than the established lower bound.<<ETX>>\",\"PeriodicalId\":208029,\"journal\":{\"name\":\"Proceedings First Asian Test Symposium (ATS `92)\",\"volume\":\"54 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-11-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"145\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings First Asian Test Symposium (ATS `92)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.1992.224429\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings First Asian Test Symposium (ATS `92)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.1992.224429","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 145

摘要

对组合电路的测试集压缩进行了研究。提出了两种主动压缩方法:强制对合并和本质故障剪枝。这两种方法加在一起，压缩测试尺寸比已知的最佳结果小20%以上，只比建立的下界大20%。

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Test set compaction for combinational circuits

Test set compaction for combinational circuits is studied. Two active compaction methods, forced pair-merging and essential fault pruning, are developed to reduce a given test set. Together these two methods, the compacted test size is smaller than known best results by more than 20% and is only 20% larger than the established lower bound.<>

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Proceedings First Asian Test Symposium (ATS `92)

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