INTEGRATING CROSSCHECK TECHNOLOGY INTO THE RAYTHEON TEST ENVIRONMENT

This paper presents our findings on inserting the CrossCheckl test technology into Raytheon's CMOS, sub-micron, sea-of-gates COMPTest gate-array product family. Crosscheck's proprietary technology coupied with our integrated CAD software environment provided extremely high test coverage accommodating complex fault models. Our evaluation of scan versus Crosscheck demonstrated that Crosscheck is a superior testmethodology. Fewer constraints were imposed on the design, a substantial reduction in tester vectors resulted, and high stuck-at NO fault coverage (>99%) was attained with relative ease. Introduction Integrated circuit complexities have risen at an exponential rate over the past decade. System requirements such as tight area constraints and substantial inter-chip signal propagation delays necessitate that more functionality be resident on a single integrated circuit. Large designs which were once 2-5 thousand gates in size are now over 100 thousand gates in size. Some projections indicate the number of gates per chip will approach 2 million by 1995. The performance requirements of integrated circuits have also been rapidly accelerating. ASIC designers today are presented with challenging projects which require the development of high speed (>50 MHz), high density ASICs in an ever shrinking design cycle window. The testability of these large, high performance circuits has become an increasing industry concern. The cost of testing these devices has become a major obstacle to their widespread use. Several surveys have been conducted to assess these cost factors. [l-41 Figure 1 illustrates a defect curve for integrated circuits. The defect level is defined as the percentage of devices which pass testing but actually contain physical defects. Crosscheck is a trademark of Crosscheck Technology, Inc. This parameter is a function of fault coverage and yield. As the graph shows, to keep the defect percentage below 0.1 percent it is necessary to achieve fault coverages in excess of 99%. With simple ad hoc fault detection techniques this has proven to be an extremely difficult achievement. As a result, structured design techniques, such as scan, have emerged in an attempt to facilitate the generation of tests which produce high fault coverage.