通过控制SiO2栅极介质中的杂质密度改善GaN mosfet的正偏置温度不稳定性

T. Yonehara, Y. Kajiwara, D. Kato, K. Uesugi, T. Shimizu, Y. Nishida, H. Ono, A. Shindome, A. Mukai, A. Yoshioka, M. Kuraguchi
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引用次数: 3

摘要

通过降低SiO2栅极介质中一定杂质密度,可以显著抑制GaN MOSFET正偏置温度不稳定性测试的阈值电压偏移。估计电荷阱能级的分析表明,栅极介质中的电子阱引起GaN mosfet的阈值电压偏移。此外,SiO2沉积后通过热处理控制了在SiO2中形成电子陷阱的杂质,并通过降低杂质密度改善了阈值电压漂移特性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Improvement of positive bias temperature instability characteristic in GaN MOSFETs by control of impurity density in SiO2 gate dielectric
Threshold voltage shift of GaN MOSFET in positive bias temperature instability test was drastically suppressed by reducing certain impurity densities in SiO2 gate dielectric. An analysis to estimate the charge trap level showed electron traps in the gate dielectric caused the threshold voltage shift in GaN MOSFETs. Moreover, impurities, which formed the electron traps in SiO2, were controlled by heat treatment after SiO2 deposition, and the threshold voltage shift characteristic was improved by the reduction of the impurity densities.
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