抑制LSI封装接地电压波动的阻抗平衡控制

Masaaki Maeda, T. Matsushima, O. Wada
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引用次数: 1

摘要

CMOS电路的同时开关电流引起功率和地反弹。电压波动被注入到CMOS衬底中,降低了电路的工作性能。在本报告中,我们重点关注CMOS衬底中的寄生耦合和电源和接地连接中的寄生电感形成桥式电路的事实,并且我们证明可以通过控制衬底电阻耦合和直流电源导体线之间插入的可变电阻来抑制电压反弹。通过四平面封装(QFP)验证了该方法的有效性,并将测量电压反弹降低了约40 dBμV。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Impedance balance control for suppression of fluctuation on ground voltage in LSI package
Simultaneous switching current of a CMOS circuit causes power and ground bounces. The voltage fluctuation is injected into the CMOS substrate, and it degrades the performance of the circuit operation. In this report, we focus on the fact that parasitic couplings in the CMOS substrate and parasitic inductance in the power and ground connection form a bridge circuit, and we demonstrate that the voltage bounce can be suppressed by controlling variable resistances that are inserted between the substrate resistive coupling and the conductor line for the DC supply. The effectiveness of this method is verified with a scaled quad flat package (QFP) and we reduced the measured voltage bounce about 40 dBμV.
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