D. V. Singh, J. Hergenrother, J. Sleight, Z. Ren, H. Nayfeh, O. Dokumaci, L. Black, D. Chidambarrao, R. Venigalla, J. Pan, B. Tessier, A. Nomura, J. Ott, M. Khare, K. Guarini, M. Ieong, W. Haensch
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Effect of contact liner stress in high-performance FDSOI devices with ultra-thin silicon channels and 30 nm gate lengths
We have investigated for the first time the effect of stressed contact liners on the performance of fully depleted ultra-thin channel CMOS devices with a raised source/drain. Significant enhancement in mobility and drive current is observed in both nFETs and pFETs. The observed enhancement shows a strong dependence on the Si channel thickness and the height of the raised source/drain, consistent with stress simulations.
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