优化Zynq fpga的GZIP压缩加速器

2019 International Semiconductor Conference (CAS) Pub Date : 2019-10-01 DOI:10.1109/smicnd.2019.8923705

Ovidiu Plugariu

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引用次数: 0

摘要

在本文中，我们介绍了我们之前设计的FPGA GZIP压缩器的结构和设计优化。最初的设计可以在I'irtexb FPGA上达到1.34 Gbps的最大吞吐量，而优化后的实现可以在Zynq-7020 FPGA上达到1.84 Gbps。硬件压缩器比运行在时钟频率为6的ARM CPU上的软件版本快8倍。7倍高。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Optimizing GZIP compression accelerator for Zynq FPGAs

In this paper we present the architecture and design optimizations brought to an FPGA GZIP compressor we previously designed. The initial design could reach a maximum throughput of 1.34 Gbps on a I'irtexb FPGA while the optimized implementation can reach up to 1.84 Gbps using a Zynq-7020 FPGA. The hardware compressor is up to 8x times faster than the software version running on an ARM CPU that has a clock frequency 6. 7x times higher.

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2019 International Semiconductor Conference (CAS)

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