cmos门内的“电阻短路”

Hong Hao, E. McCluskey
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引用次数: 145

摘要

本文研究了CMOS门内短路的影响。动态和静态栅极特性作为短路电阻的函数进行了分析。发现传播延迟增加是一种常见的动态效应。短路电阻的微小变化会使电路的性能发生剧烈变化。研究发现,由晶体管栅源短路和栅漏短路引起的故障不仅与包含故障的栅极输入有关,还与其他信号有关。由于“电阻短路”导致的模式依赖可能使使用正常TPG过程生成的测试无效。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
"RESISTIVE SHORTS" WITHIN CMOS GATES
This paper studies the effects of shorts within CMOS gates. Dynamic as well as static gate properties are analyzed as a function of the short’s resistance. Increased propagation delay is found to be a common dynamic effect. Circuit behavior can change drastically with small variations in a short’s resistance. It is found that faults caused by transistor gate-to-source and gate-to-drain shorts can be dependent not only on inputs of gates containing the faults but also on other signals. This pattern dependence due to “resistive shorts” can invalidate tests generated using normal TPG procedures.
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