基于bdd的通管逻辑SPL卡接故障的测试生成

Proceedings Sixth Asian Test Symposium (ATS'97) Pub Date : 1997-11-17 DOI:10.1109/ATS.1997.643908

T. Shinogi, T. Hayashi, K. Taki

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引用次数: 2

摘要

提出了一种通过逻辑测试生成通管逻辑压级卡死故障的测试方法。我们描述了如何使用预先计算的电压计算表来创建一个差异。为了解决表爆炸问题，我们提出了一些在实际尺寸上扩展受限制表的适用范围的技术。然后，我们提出了一个简单的DFT电路。实验结果表明了该方法的有效性。

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Test generation for stuck-on faults in BDD-based pass-transistor logic SPL

This paper presents a method of test generation for stuck-on faults in a pass-transistor logic SPL by logic testing. We describe how to create a discrepancy using a pre-computed table for voltage calculation. For solving a table explosion problem we present some techniques for extending the applicable scope of a restricted table in practical size. Then, we propose a simple DFT circuit. The experimental results show the effectiveness.

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Proceedings Sixth Asian Test Symposium (ATS'97)

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