{"title":"二进制序号的多次加法","authors":"L. Dadda","doi":"10.1109/ARITH.1978.6155772","DOIUrl":null,"url":null,"abstract":"It is shown how circuits for the addition of several serial binary numbers can be obtained as a combination of parallel counters and memory cells. The various schemes belong to one of three different classes, characterized by the way in which carries, produced by parallel counters, are treated. A comparison is made between the various schemes, in terms of speed and complexity.","PeriodicalId":443215,"journal":{"name":"1978 IEEE 4th Symposium onomputer Arithmetic (ARITH)","volume":"610 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1978-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"Multiple addition of binary serial numbers\",\"authors\":\"L. Dadda\",\"doi\":\"10.1109/ARITH.1978.6155772\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"It is shown how circuits for the addition of several serial binary numbers can be obtained as a combination of parallel counters and memory cells. The various schemes belong to one of three different classes, characterized by the way in which carries, produced by parallel counters, are treated. A comparison is made between the various schemes, in terms of speed and complexity.\",\"PeriodicalId\":443215,\"journal\":{\"name\":\"1978 IEEE 4th Symposium onomputer Arithmetic (ARITH)\",\"volume\":\"610 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1978-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1978 IEEE 4th Symposium onomputer Arithmetic (ARITH)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ARITH.1978.6155772\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1978 IEEE 4th Symposium onomputer Arithmetic (ARITH)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ARITH.1978.6155772","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
It is shown how circuits for the addition of several serial binary numbers can be obtained as a combination of parallel counters and memory cells. The various schemes belong to one of three different classes, characterized by the way in which carries, produced by parallel counters, are treated. A comparison is made between the various schemes, in terms of speed and complexity.